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Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs., , , , , and . DATE, page 37-42. IEEE, (2020)Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators., , , , , , and . CoRR, (2020)Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools - Part 2., and . IEEE Des. Test, 33 (2): 7-8 (2016)Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs., and . J. Inform. and Commun. Convergence Engineering, (2015)Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing., , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (7): 565-569 (2009)Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches., , , and . Microprocess. Microsystems, (2016)TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (8): 1194-1207 (2012)Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (11): 1694-1707 (2013)Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (12): 1964-1976 (2015)Retiming-based timing analysis with an application to mincut-based global placement., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (12): 1684-1692 (2004)