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A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.

B. Liu, H. Ngo, K. Nakata, W. Deng, Y. Zhang, J. Qiu, T. Yoshioka, J. Emmei, H. Zhang, J. Pang, A. Narayanan, D. Yang, H. Liu, K. Okada, and A. Matsuzawa. CICC, page 1-4. IEEE, (2018)

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Junjun Chen

JunJun Pan

Xiuhui Qiu

Wei Qiu

Xueping Qiu

Other publications of authors with the same name

A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter.Y. Zhang, Z. Sun, B. Liu, J. Qiu, D. Xu, Y. Zhang, X. Fu, D. You, H. Huang, W. Madany and 6 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference.D. Xu, Y. Zhang, H. Huang, Z. Sun, B. Liu, A. Fadila, J. Qiu, Z. Liu, W. Wang, Y. Xiong and 3 other author(s). CICC, page 1-2. IEEE, (2023)A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration.J. Qiu, W. Wang, Z. Sun, B. Liu, Y. Zhang, D. Xu, H. Huang, A. Fadila, Z. Liu, W. Madany and 3 other author(s). ISSCC, page 80-81. IEEE, (2023)10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.D. Xu, Z. Liu, Y. Kuai, H. Huang, Y. Zhang, Z. Sun, B. Liu, W. Wang, Y. Xiong, J. Qiu and 5 other author(s). ISSCC, page 192-194. IEEE, (2024)A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.B. Liu, H. Ngo, K. Nakata, W. Deng, Y. Zhang, J. Qiu, T. Yoshioka, J. Emmei, H. Zhang, J. Pang and 5 other author(s). CICC, page 1-4. IEEE, (2018)A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR.J. Pang, Z. Li, R. Kubozoe, X. Luo, R. Wu, Y. Wang, D. You, A. Fadila, R. Saengchan, T. Nakamura and 16 other author(s). IEEE J. Solid State Circuits, 55 (9): 2371-2386 (2020)A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration.B. Liu, Y. Zhang, J. Qiu, H. Ngo, W. Deng, K. Nakata, T. Yoshioka, J. Emmei, J. Pang, A. Narayanan and 4 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 603-616 (2021)A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS.Y. Wang, R. Wu, J. Pang, D. You, A. Fadila, R. Saengchan, X. Fu, D. Matsumoto, T. Nakamura, R. Kubozoe and 12 other author(s). IEEE J. Solid State Circuits, 55 (5): 1249-1269 (2020)32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth.J. Qiu, Z. Sun, B. Liu, W. Wang, D. Xu, H. Herdian, H. Huang, Y. Zhang, Y. Wang, A. Shirane and 1 other author(s). ISSCC, page 454-456. IEEE, (2021)An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration.B. Liu, Y. Zhang, J. Qiu, W. Deng, Z. Xu, H. Zhang, J. Pang, Y. Wang, R. Wu, T. Someya and 2 other author(s). CICC, page 1-4. IEEE, (2019)

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Disambiguation of "Qiu, Junjun"

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A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.

Please choose a person to relate this publication to

Junjun Chen

JunJun Pan

Xiuhui Qiu

Wei Qiu

Xueping Qiu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Qiu, Junjun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.

Please choose a person to relate this publication to

Junjun Chen

JunJun Pan

Xiuhui Qiu

Wei Qiu

Xueping Qiu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.