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A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques.

, , , , , , , , , , и . IEEE J. Solid State Circuits, 48 (10): 2558-2569 (2013)

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Wu Wen

Wen Wu

Chin-Yi Wu

Chin-Yi Wu

Wen-Zhong Wu

 

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