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Disambiguation of "Jain, Abhishek Kumar"

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Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?

, , and . DASC/PiCom/DataCom/CyberSciTech, page 586-593. IEEE Computer Society, (2016)

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Abhishek Jain

Abhishek Kumar

Abhishek Kumar

Kumar Abhishek Sinha

Mohinder Kumar Jain

 

Other publications of authors with the same name

High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay., , , , and . ISCAS, page 1-5. IEEE, (2020)Role of on-chip networks in building domain-specific architectures (DSAs) for sparse computations (invited).. SLIP, page 9. ACM, (2020)Throughput oriented FPGA overlays using DSP blocks., , and . DATE, page 1628-1633. IEEE, (2016)Architecture centric coarse-grained FPGA overlays. Nanyang Technological University, Singapore, (2017)A time-multiplexed FPGA overlay with linear interconnect., , , and . DATE, page 1075-1080. IEEE, (2018)DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect., , , , and . FCCM, page 1-8. IEEE Computer Society, (2016)Efficient Overlay Architecture Based on DSP Blocks., , and . FCCM, page 25-28. IEEE Computer Society, (2015)A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs., , , , , and . FPL, page 127-132. IEEE, (2020)Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs., , , , , , and . FCCM, page 133-143. IEEE, (2023)Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?, , and . DASC/PiCom/DataCom/CyberSciTech, page 586-593. IEEE Computer Society, (2016)