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Disambiguation of "Keane, John P."

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Towards a learning organisation: the application of process-based knowledge maps to asset management (a case study)

, , and . Knowledge and Process Management, 14 (2): 131--143 (2007)

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John P Burrows

John P Brown

John P Broussard

John P Teschke

John P Dickson

 

Other publications of authors with the same name

Digital background calibration for memory effects in pipelined analog-to-digital converters., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (3): 511-525 (2006)16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving -58dBFS noise and 4GHz bandwidth in 28nm CMOS., , , , , , , and . ISSCC, page 284-285. IEEE, (2017)A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction., , , , , , , , , and 6 other author(s). ISSCC, page 466-467. IEEE, (2013)Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (2): 275-285 (2004)An adaptive analog noise-predictive decision-feedback equalizer., , and . IEEE J. Solid State Circuits, 37 (2): 105-113 (2002)Analog timing recovery for a noise-predictive decision-feedback equalizer., , and . IEEE J. Solid State Circuits, 38 (2): 338-342 (2003)Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC)., , , , and . IEEE J. Solid State Circuits, 55 (12): 3127-3130 (2020)Towards a learning organisation: the application of process-based knowledge maps to asset management (a case study), , and . Knowledge and Process Management, 14 (2): 131--143 (2007)Background interstage gain calibration technique for pipelined ADCs., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (1): 32-43 (2005)