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Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective., and . ICCD, page 209-213. IEEE Computer Society, (2001)A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS., , , , , and . ISSCC, page 136-137. IEEE, (2013)Design and Analysis of Low-Voltage Current-Mode Logic Buffers.. ISQED, page 293-298. IEEE Computer Society, (2003)Subspace-Based Suppression of Cortical Stimulation Artifacts., , , , and . EMBC, page 2426-2429. IEEE, (2018)Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA.. IEEE J. Solid State Circuits, 42 (9): 1892-1905 (2007)A Study of BER and EVM Degradation in Digital Modulation Schemes Due to PLL Jitter and Communication-Link Noise., and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (8): 3402-3415 (2022)On the Dynamics of Regenerative Frequency Dividers., , and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (12): 1413-1417 (2006)Invited - Integrated millimeter-wave/terahertz sensor systems for near-field IoT.. DAC, page 144:1-144:6. ACM, (2016)A Distributed RF Front-End for UWB Receivers., , and . CICC, page 805-808. IEEE, (2006)A Current-Equalized Distributed Receiver Front-End for UWB Direct Conversion Receivers., , and . CICC, page 535-538. IEEE, (2007)