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Disambiguation of "Ohhata, Kenichi"

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A High-Time-Resolution Time-to-Digital Converter Using Coupled Ring Oscillator with Phase Averaging.

, , , and . APCCAS, page 195-198. IEEE, (2022)

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Kenichi Ishikawa

Kenichi Kida

Kenichi Moriya

Kenichi Okuda

Kenichi Kumatani

 

Other publications of authors with the same name

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 35 (4): 564-571 (2000)A wide-dynamic-range, high-transimpedance Si bipolar preamplifier IC for 10-Gb/s optical fiber links., , , , and . IEEE J. Solid State Circuits, 34 (1): 18-24 (1999)Automatic technique of distortion compensation in resistor ladder for high-speed and low-power ADC., and . IEICE Electron. Express, 11 (11): 20140313 (2014)Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-µm CMOS Technology., , , and . IEICE Trans. Electron., 89-C (2): 203-205 (2006)A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC.. IEEE J. Solid State Circuits, 54 (7): 2038-2048 (2019)17 Gb/s VCSEL driver using double-pulse asymmetric emphasis technique in 90-nm CMOS for optical interconnection., , , , , , and . ISCAS, page 1847-1850. IEEE, (2010)A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 30 (4): 491-499 (April 1995)Low-Offset, Low-Power Latched Comparator Using Capacitive Averaging Technique., , and . IEICE Trans. Electron., 94-C (12): 1889-1895 (2011)A 2.3-MW, 950-MHz, 8-Bit Fully-Time-Based Subranging ADC Using Highly-Linear Dynamic VTC.. VLSI Circuits, page 95-96. IEEE, (2018)SiGe-HBT-based 54-gb/s 4: 1 multiplexer IC with full-rate clock for serial communication systems., , , , , , , , , and . IEEE J. Solid State Circuits, 40 (3): 791-795 (2005)