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Disambiguation of "Jiang, Bentian"

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A fast machine learning-based mask printability predictor for OPC acceleration.

, , , and . ASP-DAC, page 412-419. ACM, (2019)

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Ping Jiang

Jiang Yi

Xin Jiang

Kaiyun Jiang

Qiu Jiang

 

Other publications of authors with the same name

Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (8): 2671-2684 (2022)Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (9): 3067-3077 (September 2023)Detailed routing by sparse grid graph and minimum-area-captured path search., , , , , and . ASP-DAC, page 754-760. ACM, (2019)Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization., , , , , and . ICCAD, page 20:1-20:9. IEEE, (2020)FIT: Fill Insertion Considering Timing., , , , , , , and . DAC, page 221. ACM, (2019)A fast machine learning-based mask printability predictor for OPC acceleration., , , and . ASP-DAC, page 412-419. ACM, (2019)CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel Sizing., , , , , , and . ICCAD, page 142:1-142:9. IEEE, (2020)Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (8): 2426-2439 (August 2024)CU.POKer: Placing DNNs on WSE With Optimal Kernel Sizing and Efficient Protocol Optimization., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (6): 1888-1901 (2022)Building up End-to-end Mask Optimization Framework with Self-training., , , and . ISPD, page 63-70. ACM, (2021)