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Disambiguation of "Balakrishnan, Kedarnath J."

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Test cost reduction for SoC using a combined approach to test data compression and test scheduling.

, and . DATE, page 39-44. EDA Consortium, San Jose, CA, USA, (2007)

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Sangeetha Balakrishnan

Balakrishnan Venkatesh

Karthikeyan Balakrishnan

Veeramuthu Balakrishnan

Karthik Balakrishnan

 

Other publications of authors with the same name

X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors., , and . IEEE Trans. Computers, 57 (7): 978-989 (2008)Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination., and . DATE, page 1130-1135. IEEE Computer Society, (2005)Scan-Based BIST Diagnosis Using an Embedded Processor., and . DFT, page 209-216. IEEE Computer Society, (2003)Relating entropy theory to test data compression., and . ETS, page 94-99. IEEE Computer Society, (2004)Test access mechanism for multiple identical cores., , , , and . ITC, page 1-10. IEEE Computer Society, (2009)Compressing Functional Tests for Microprocessors., , and . Asian Test Symposium, page 428-433. IEEE Computer Society, (2005)PIDISC: Pattern Independent Design Independent Seed Compression Technique., , and . VLSI Design, page 811-817. IEEE Computer Society, (2006)Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding.. VLSI Design, page 345-350. IEEE Computer Society, (2007)Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion., and . ITC, page 936-944. IEEE Computer Society, (2004)Test cost reduction for SoC using a combined approach to test data compression and test scheduling., and . DATE, page 39-44. EDA Consortium, San Jose, CA, USA, (2007)