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System and Design Technology Co-Optimization of SOT-MRAM for High-Performance AI Accelerator Memory System., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1065-1078 (April 2024)Designing Efficient and High-performance AI Accelerators with Customized STT-MRAM., and . CoRR, (2021)True Random Number Generation using Latency Variations of Commercial MRAM Chips., , , and . ISQED, page 510-515. IEEE, (2021)System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning., and . ACM Great Lakes Symposium on VLSI, page 697-702. ACM, (2023)A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs., , and . VTS, page 1-6. IEEE Computer Society, (2015)Attacking Deep Learning AI Hardware with Universal Adversarial Perturbation., , , and . CoRR, (2021)Design of Reliable SoCs With BIST Hardware and Machine Learning., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (11): 3237-3250 (2017)SNNLP: Energy-Efficient Natural Language Processing Using Spiking Neural Networks., , , and . CoRR, (2024)Special Session: Reliability Analysis for AI/ML Hardware., , , , , , and . VTS, page 1-10. IEEE, (2021)Special Session: On the Reliability of Conventional and Quantum Neural Network Hardware., , , , , , , and . VTS, page 1-12. IEEE, (2022)