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Disambiguation of "Zhou, Dian"

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An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture.

, , , , , and . ASICON, page 389-392. IEEE, (2011)

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Dian Handayani

Zhou Zhou

Mahmud Dianati

Nadja Diane

Marco Alberto Diana

 

Other publications of authors with the same name

FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp., , , and . ASICON, page 1-4. IEEE, (2013)An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles., and . ISCAS (6), page 258-261. IEEE, (1999)RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect., , , and . ISCAS, page 2710-2713. IEEE, (2007)Propagation Delay in RLC Interconnection Networks., and . ISCAS, page 2125-2128. IEEE, (1993)Frequency driven repeater insertion for deep submicron., , , and . ISCAS (5), page 181-184. IEEE, (2004)Optimization of VLSI Allocation., and . ISCAS, page 1065-1068. IEEE, (1995)Efficient SVM-based hotspot detection using spectral clustering., , , and . ISCAS, page 1-4. IEEE, (2017)Implementations of FFT and STBD for MIMO-OFDM on a Reconfigurable Baseband Platform., , , , and . IEICE Trans. Inf. Syst., 93-D (4): 811-821 (2010)An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (6): 1954-1967 (2018)An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling., , , , , and . DATE, page 67-72. IEEE, (2020)