Avalda FPGA Developer compiles "quoted" F# programs. Quotations are a feature in F# in which you wrap an F# expression in the quotation operators "<@@" and "@@>" so that the expression is treated like data and can be manipulated as such. The Avalda FPGA Developer api then allows the quoted expression to be translated to an XML encoding suitable for the core Avalda FPGA Developer compiler tool. So, write the following program and go to "Build" -> "Build GCDTutorial" to build a dll called gcdtutorial.dll: #light "off" namespace GCDTutorial type GCD = class static member gcdprogram = <@@ let rec gcd( (m : int), (n : int) ) = if m = 0 then n else gcd( n % m, m) in () @@> end
Chuck Thacker is building a new research computer called the BEE3. There was a time, years ago, when computer architecture was a most exciting area to explore. Talented, young computer scientists labored on the digital frontier to devise the optimal design, structure, and implementation of computer systems. The crux of that work led directly to the PC revolution from which hundreds of millions benefit today. Computer architecture was sexy. These days? Not so much. But Chuck Thacker aims to change that.
A Tiny Computer. An unpublished memo by Chuck Thacker, Microsoft Research, 3 September 2007. Posted with permission. Alan Kay recently posed the following problem: "I'd like to show JHS and HS kids 'the simplest non-tricky architecture' in which simple gates and flipflops manifest a programmable computer”. Alan posed a couple of other desiderata, primarily that the computer needs to demonstrate fundamental principles, but should be capable of running real programs produced by a compiler. This introduces some tension into the design, since simplicity and performance sometimes are in conflict. This sounded like an interesting challenge, and I have a proposed design. Presents the design of a complete CPU in under two pages of FPGA-ready Verilog. The TC3 is a Harvard architecture 32-bit RISC with 1KB of instruction memory, 1KB of data memory, and 128 general-purpose registers. This design is an ancestor of the DDR2 DRAM Controller used in the BEE3.