%0 Journal Article %1 journals/tcas/Ma0GR19 %A Ma, Shunli %A Yu, Hao %A Gu, Qun Jane %A Ren, Junyan %D 2019 %J IEEE Trans. Circuits Syst. I Regul. Pap. %K dblp %N 2 %P 555-568 %T A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package. %U http://dblp.uni-trier.de/db/journals/tcas/tcasI66.html#Ma0GR19 %V 66-I

@article{journals/tcas/Ma0GR19, added-at = {2020-05-22T00:00:00.000+0200}, author = {Ma, Shunli and Yu, Hao and Gu, Qun Jane and Ren, Junyan}, biburl = {https://www.bibsonomy.org/bibtex/2b9ddb394c455588a8ca00d354490cd1e/dblp}, ee = {https://doi.org/10.1109/TCSI.2018.2867623}, interhash = {b5596e0084aedb8e3546eb4edd5a1ada}, intrahash = {b9ddb394c455588a8ca00d354490cd1e}, journal = {IEEE Trans. Circuits Syst. I Regul. Pap.}, keywords = {dblp}, number = 2, pages = {555-568}, timestamp = {2020-05-23T12:30:04.000+0200}, title = {A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasI66.html#Ma0GR19}, volume = {66-I}, year = 2019 }