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Disambiguation of "Ren, Junyan"

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A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package.

, , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (2): 555-568 (2019)

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Junyan Zhu

Zhongliang Ren

Jianxin Ren

Hongming Ren

Ling Ren

 

Other publications of authors with the same name

A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation., , , , and . APCCAS, page 128-131. IEEE, (2012)A DLL based low-phase-noise clock multiplier with offset-tolerant PFD., , and . ASICON, page 1-4. IEEE, (2013)A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs., , , , and . ASICON, page 295-298. IEEE, (2017)A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error., , and . ASICON, page 32-35. IEEE, (2017)A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio., , , , , and . ISCAS, page 1145-1148. IEEE, (2011)Automatic gain control algorithm with high-speed and double closed-loop in UWB system., , , , and . ASICON, page 1-4. IEEE, (2013)A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic., , , and . APCCAS, page 42-45. IEEE, (2018)A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (2): 233-242 (February 2023)Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_cm$ -Based Switching., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 1168-1172 (2017)A Monolithic Sub-sampling PLL based 6-18 GHz Frequency Synthesizer for C, X, Ku Band Communication., , , , , and . IEICE Trans. Electron., 98-C (1): 16-27 (2015)