%0 Conference Paper %1 conf/isscc/AhmadUISASCF16 %A Ahmad, Fazil %A Unruh, Greg %A Iyer, Amrutha %A Su, Pin-En %A Abdalla, Sherif %A Shen, Bo %A Chambers, Mark %A Fujimori, Ichiro %B ISSCC %D 2016 %I IEEE %K dblp %P 324-325 %T 19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC. %U http://dblp.uni-trier.de/db/conf/isscc/isscc2016.html#AhmadUISASCF16 %@ 978-1-4673-9467-3

@inproceedings{conf/isscc/AhmadUISASCF16, added-at = {2016-03-02T00:00:00.000+0100}, author = {Ahmad, Fazil and Unruh, Greg and Iyer, Amrutha and Su, Pin-En and Abdalla, Sherif and Shen, Bo and Chambers, Mark and Fujimori, Ichiro}, biburl = {https://www.bibsonomy.org/bibtex/22df6a33a6eff9164c79237a531d1ede7/dblp}, booktitle = {ISSCC}, crossref = {conf/isscc/2016}, ee = {http://dx.doi.org/10.1109/ISSCC.2016.7418038}, interhash = {cab79b51c945290ab59ec45900d39307}, intrahash = {2df6a33a6eff9164c79237a531d1ede7}, isbn = {978-1-4673-9467-3}, keywords = {dblp}, pages = {324-325}, publisher = {IEEE}, timestamp = {2016-03-03T11:43:08.000+0100}, title = {19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.}, url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2016.html#AhmadUISASCF16}, year = 2016 }