%0 Journal Article %1 journals/tcad/ReshadiGD06 %A Reshadi, Mehrdad %A Gorjiara, Bita %A Dutt, Nikil D. %D 2006 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 12 %P 2904-2918 %T Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators. %U http://dblp.uni-trier.de/db/journals/tcad/tcad25.html#ReshadiGD06 %V 25

@article{journals/tcad/ReshadiGD06, added-at = {2020-09-24T00:00:00.000+0200}, author = {Reshadi, Mehrdad and Gorjiara, Bita and Dutt, Nikil D.}, biburl = {https://www.bibsonomy.org/bibtex/2a170cc7b3bfd2ffe1feace0a1fba112a/dblp}, ee = {https://doi.org/10.1109/TCAD.2006.882597}, interhash = {e4f1d072918915cdc8ec20aa8d95237e}, intrahash = {a170cc7b3bfd2ffe1feace0a1fba112a}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 12, pages = {2904-2918}, timestamp = {2020-09-25T11:49:28.000+0200}, title = {Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad25.html#ReshadiGD06}, volume = 25, year = 2006 }