Author of the publication

Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2904-2918 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Memory architecture exploration for programmable embedded systems., , and . Kluwer, (2003)Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements., , , , , , , and . PARCO, volume 15 of Advances in Parallel Computing, page 767-776. IOS Press, (2007)Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures., , , and . DIPES, volume 271 of IFIP, page 213-225. Springer, (2008)Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation, and . CoRR, (2007)ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement, , , , and . CoRR, (2007)Design Methodology for Responsive and Rrobust MIMO Control of Heterogeneous Multicores., , , , , and . IEEE Trans. Multi Scale Comput. Syst., 4 (4): 944-951 (2018)System-level PVT variation-aware power exploration of on-chip communication architectures., , , and . ACM Trans. Design Autom. Electr. Syst., 14 (2): 20:1-20:25 (2009)NoC-based fault-tolerant cache design in chip multiprocessors., , and . ACM Trans. Embed. Comput. Syst., 13 (3s): 115:1-115:26 (2014)Fast Configurable-Cache Tuning With a Unified Second-Level Cache., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (1): 80-91 (2009)Real-time analysis of resource-constrained distributed systems by simulation-guided model checking., and . SIGBED Rev., 5 (1): 7 (2008)