%0 Journal Article %1 journals/jssc/KhellahSYKHRSTB07 %A Khellah, Muhammad M. %A Somasekhar, Dinesh %A Ye, Yibin %A Kim, Nam-Sung %A Howard, Jason %A Ruhl, Gregory %A Sunna, Murad %A Tschanz, James W. %A Borkar, Nitin %A Hamzaoglu, Fatih %A Pandya, Gunjan %A Farhang, Ali %A Zhang, Kevin %A De, Vivek %D 2007 %J IEEE J. Solid State Circuits %K dblp %N 1 %P 233-242 %T A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. %U http://dblp.uni-trier.de/db/journals/jssc/jssc42.html#KhellahSYKHRSTB07 %V 42

@article{journals/jssc/KhellahSYKHRSTB07, added-at = {2022-10-02T00:00:00.000+0200}, author = {Khellah, Muhammad M. and Somasekhar, Dinesh and Ye, Yibin and Kim, Nam-Sung and Howard, Jason and Ruhl, Gregory and Sunna, Murad and Tschanz, James W. and Borkar, Nitin and Hamzaoglu, Fatih and Pandya, Gunjan and Farhang, Ali and Zhang, Kevin and De, Vivek}, biburl = {https://www.bibsonomy.org/bibtex/2bacebad423fb0534d65cbf750ad272a4/dblp}, ee = {https://doi.org/10.1109/JSSC.2006.888357}, interhash = {f7b6488227278110d8c9945f15d47318}, intrahash = {bacebad423fb0534d65cbf750ad272a4}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 1, pages = {233-242}, timestamp = {2024-04-08T10:44:22.000+0200}, title = {A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc42.html#KhellahSYKHRSTB07}, volume = 42, year = 2007 }