%0 Journal Article %1 journals/jssc/SuzukiYYSA08 %A Suzuki, Toshikazu %A Yamauchi, Hiroyuki %A Yamagami, Yoshinobu %A Satomi, Katsuji %A Akamatsu, Hironori %D 2008 %J IEEE J. Solid State Circuits %K dblp %N 9 %P 2109-2119 %T A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses. %U http://dblp.uni-trier.de/db/journals/jssc/jssc43.html#SuzukiYYSA08 %V 43

@article{journals/jssc/SuzukiYYSA08, added-at = {2024-05-07T00:00:00.000+0200}, author = {Suzuki, Toshikazu and Yamauchi, Hiroyuki and Yamagami, Yoshinobu and Satomi, Katsuji and Akamatsu, Hironori}, biburl = {https://www.bibsonomy.org/bibtex/2fcec5fcea7f6dbc6dfda44a98ff4f745/dblp}, ee = {https://doi.org/10.1109/JSSC.2008.2001872}, interhash = {fdefa0647a8ea018cb9ee7d477bab75a}, intrahash = {fcec5fcea7f6dbc6dfda44a98ff4f745}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 9, pages = {2109-2119}, timestamp = {2024-05-13T07:04:34.000+0200}, title = {A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc43.html#SuzukiYYSA08}, volume = 43, year = 2008 }