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Disambiguation of "Yamauchi, Hiroyuki"

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A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses.

, , , , and . IEEE J. Solid State Circuits, 43 (9): 2109-2119 (2008)

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Hiroyuki Tan

Hiroyuki Kobayashi

Hiroyuki Okamuro

Hiroyuki Takada

Hiroyuki Isobe

 

Other publications of authors with the same name

Multi-Layer Logic - A Predicate Logic Including Data Structure as Knowledge Representation Language., and . New Generation Comput., 3 (4): 403-439 (1985)An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (3): 864-877 (2013)A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies.. IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 763-774 (2010)0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier., , , , , and . IEICE Trans. Electron., 88-C (4): 630-638 (2005)A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 40 (11): 2296-2304 (2005)Errors in solving inverse problem for reversing RTN effects on VCCmin shift in SRAM reliability screening test designs., and . SoCC, page 318-323. IEEE, (2014)17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme., , , , , and . ISSCC, page 1-3. IEEE, (2015)Development and operation of GIS exercise materials for undergraduate students., , , and . PeerJ PrePrints, (2018)A Method and Language for Constructing Multiagent Systems., and . ISMIS, volume 1932 of Lecture Notes in Computer Science, page 619-628. Springer, (2000)A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme., , , , , , and . IEEE J. Solid State Circuits, 52 (9): 2498-2514 (2017)