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Disambiguation of "Akamatsu, Hironori"

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A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses.

, , , , and . IEEE J. Solid State Circuits, 43 (9): 2109-2119 (2008)

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Hironori Kumeno

Hironori Tokuno

 

Other publications of authors with the same name

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 43 (1): 180-191 (2008)A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses., , , , and . IEEE J. Solid State Circuits, 43 (9): 2109-2119 (2008)A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture., , , and . IEEE Trans. Very Large Scale Integr. Syst., 5 (4): 377-387 (1997)A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme., , , and . CICC, page 233-236. IEEE, (2007)A 256-Mb DRAM with 100 MHz serial I/O ports for storage of moving pictures., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 29 (11): 1310-1316 (November 1994)0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier., , , , , and . IEICE Trans. Electron., 88-C (4): 630-638 (2005)A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations., , , , , , , , , and 6 other author(s). ISSCC, page 326-606. IEEE, (2007)A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 43 (4): 938-945 (2008)A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes., , , and . ISLPED, page 49-54. IEEE, (1996)An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's., , and . IEEE J. Solid State Circuits, 30 (4): 423-431 (April 1995)