@article{journals/jssc/KobayashiNKNMTOAHMY94,
added-at = {2023-05-04T00:00:00.000+0200},
author = {Kobayashi, Shin'ichi and Nakai, Hiroaki and Kunori, Yuichi and Nakayama, Takeshi and Miyawaki, Yoshikazu and Terada, Yasushi and Onoda, Hiroshi and Ajika, Natsuo and Hatanaka, Masahiro and Miyoshi, Hirokazu and Yoshihara, Tsutomu},
biburl = {https://www.bibsonomy.org/bibtex/28d24a29d1311563d9edf12f951257ebd/dblp},
ee = {https://doi.org/10.1109/4.280695},
interhash = {bf56c9f2b55a78dfced2c58e80b9ff12},
intrahash = {8d24a29d1311563d9edf12f951257ebd},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
month = {April},
number = 4,
pages = {454-460},
timestamp = {2024-04-08T10:44:07.000+0200},
title = {Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc29.html#KobayashiNKNMTOAHMY94},
volume = 29,
year = 1994
}