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Disambiguation of "Nakayama, Takeshi"

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Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 29 (4): 454-460 (April 1994)

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Takeshi Morita

Kanzo Nakayama

Yoshihiro Nakayama

Nobushige Nakayama

Takeshi Morita

 

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Non-restraint human authentication using MIMO array., , , and . IPIN (Short Papers/Work-in-Progress Papers), volume 2498 of CEUR Workshop Proceedings, page 408-415. CEUR-WS.org, (2019)A model-based approach for recognizing folding process of origami., , , , and . ICPR, page 1808-1811. IEEE Computer Society, (1998)Identifying contents page of documents., , and . ICPR, page 696-700. IEEE Computer Society, (1996)RSSI-Based Living-Body Radar Using Single RF Front-End and Tunable Parasitic Antennas., , , and . IEICE Trans. Commun., 101-B (2): 392-399 (2018)Estimation Method of the Number of Targets Using Cooperative Multi-Static MIMO Radar., , , , and . IEICE Trans. Commun., 104-B (12): 1539-1546 (2021)A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 34 (11): 1544-1550 (1999)Tiling algorithm with fitting violation function for analog neural array., , and . ICNN, page 565-570. IEEE, (1996)Neural network approach to traveling salesman problem based on hierarchical city adjacency., , , and . ICNN, page 2626-2631. IEEE, (1995)Human Activity Identification by Height and Doppler RCS Information Detected by MIMO Radar., , , and . IEICE Trans. Commun., 102-B (7): 1270-1278 (2019)Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 29 (4): 454-460 (April 1994)