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Navigating SMEs' Innovation in the Digital Age: From Manufacturing to Servitization., , , and . AMCIS, Association for Information Systems, (2023)27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking., , , , , , , , , and 12 other author(s). ISSCC, page 452-453. IEEE, (2014)Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier., , , , , , and . ISVLSI, page 316-321. IEEE Computer Society, (2008)Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects., , , , , and . ISVLSI, page 615-620. IEEE Computer Society, (2015)2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters., , , , , , , , , and 18 other author(s). ISSCC, page 46-48. IEEE, (2020)Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization., , , , , , and . Microelectron. J., 42 (5): 718-732 (2011)A Microprogrammable Memory Controller for high-performance dataflow applications., , , and . ESSCIRC, page 348-351. IEEE, (2009)A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 50 (1): 125-136 (2015)IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management., , , , , , , , , and 18 other author(s). IEEE J. Solid State Circuits, 56 (1): 79-97 (2021)Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities., , , , , , and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 266-275. Springer, (2009)