Author of the publication

A 1-16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector.

, and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (8): 487-491 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 2.4GHz Efficiency-Enhanced Rectifier for Wireless Telemetry., , and . CICC, page 555-558. IEEE, (2007)A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient., and . IEEE Trans. Very Large Scale Integr. Syst., 27 (3): 501-510 (2019)A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor., and . IEEE Trans. Very Large Scale Integr. Syst., 27 (11): 2698-2702 (2019)A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector., and . IEICE Trans. Electron., 88-C (8): 1726-1730 (2005)A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology., and . IEICE Trans. Electron., 89-C (3): 295-299 (2006)A Leakage-Compensated PLL in 65-nm CMOS Technology., and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (7): 525-529 (2009)CMOS current-mode divider and its applications., , and . IEEE Trans. Circuits Syst. II Express Briefs, 52-II (3): 145-148 (2005)A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider., , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (7): 555-559 (2009)A PVT-Tolerant Injection-Locked Clock Multiplier With a Frequency Calibrator Using a Delay Time Detector., and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (2): 177-181 (2019)A 3-8 GHz Delay-Locked Loop With Cycle Jitter Calibration., and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (11): 1094-1098 (2008)