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A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only)., and . FPGA, page 289. ACM, (2010)An Efficient SAT-Attack Algorithm Against Logic Encryption., and . IOLTS, page 44-47. IEEE, (2019)Multi-operand adder synthesis on FPGAs using generalized parallel counters., , and . ASP-DAC, page 337-342. IEEE, (2010)Binding Refinement for Multiplexer Reduction., and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs., and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)A Hardware Maze Router with Application to Interactive Rip-Up and Reroute., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 5 (4): 466-476 (1986)A New Algorithm for Boolean Matching Utilizing Structural Information.. IEICE Trans. Inf. Syst., 78-D (3): 219-223 (1995)Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (12): 3451-3460 (2008)An Efficient Equivalence Checker for Combinational Circuits.. DAC, page 629-634. ACM Press, (1996)Development of practical ATPG tool with flexible interface., and . ATS, page 129. IEEE, (2006)