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Disambiguation of "Ohtsuki, Tatsuo"

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A Hardware Maze Router with Application to Interactive Rip-Up and Reroute.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 5 (4): 466-476 (1986)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Takashi Ohtsuki

Tatsuo Oguro

Tatsuo Oguro

Tatsuo Oguro

Tatsuo Oguro

 

Other publications of authors with the same name

Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2481-2489 (2010)A Hardware Maze Router with Application to Interactive Rip-Up and Reroute., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 5 (4): 466-476 (1986)Area/delay estimation for digital signal processor cores., , , , and . ASP-DAC, page 156-161. ACM, (2001)An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays., , , and . ASP-DAC, page 519-526. IEEE, (1998)High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (4): 827-834 (2002)The two disjoint path problem and wire routing design.. Graph Theory and Algorithms, volume 108 of Lecture Notes in Computer Science, page 207-216. Springer, (1980)A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (12): 3514-3523 (2008)A Two-Level Cache Design Space Exploration System for Embedded Applications., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (12): 3238-3247 (2009)X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (12): 3119-3127 (2009)Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (4): 996-1004 (2006)