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Disambiguation of "Hashizume, Masaki"

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Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits.

, , and . IEICE Trans. Inf. Syst., 87-D (3): 571-579 (2004)

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Keiko Hashizume

Masaki Nakajima

 

Other publications of authors with the same name

A built-in test circuit for open defects at interconnects between dies in 3D ICs., , , , and . 3DIC, page 1-5. IEEE, (2011)Efficient test length reduction techniques for interposer-based 2.5D ICs., , , , and . VLSI-DAT, page 1-4. IEEE, (2014)Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs., , , and . IEEE Trans. Computers, 64 (5): 1230-1240 (2015)Fault Detection of Combinational Circuits Based on Supply Current., , , and . ITC, page 374-380. IEEE Computer Society, (1988)Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits., , and . IEICE Trans. Inf. Syst., 87-D (3): 571-579 (2004)On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan., , , and . IEICE Trans. Inf. Syst., 96-D (9): 1986-1993 (2013)Identification of Feedback Bridging Faults with Oscillation., , and . Asian Test Symposium, page 25-. IEEE Computer Society, (1999)Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code., , and . Asian Test Symposium, page 163-166. IEEE Computer Society, (2010)New Class of Tests for Open Faults with Considering Adjacent Lines., , , , , , and . Asian Test Symposium, page 301-306. IEEE Computer Society, (2009)Test Time Reduction for I DDQ Testing by Arranging Test Vectors., , and . Asian Test Symposium, page 423-428. IEEE Computer Society, (2002)