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A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing.

, , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)

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Power-aware test generation with guaranteed launch safety for at-speed scan testing., , , , , , , and . VTS, page 166-171. IEEE Computer Society, (2011)Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications., , , and . DATE, page 1679-1684. IEEE, (2019)Power supply noise and its reduction in at-speed scan testing.. ASICON, page 1-4. IEEE, (2015)Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 17 (4): 48:1-48:16 (2012)Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing., , , , , and . DAC, page 527-532. IEEE, (2007)Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets., , , , , , and . IEEE Access, (2019)Efficient Guided-Probe Fault Location Method for Sequential Circuits., , , and . IEICE Trans. Inf. Syst., 78-D (2): 122-129 (1995)Efficient Test Set Modification for Capture Power Reduction., , , , , , and . J. Low Power Electron., 1 (3): 319-330 (2005)Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns., , , , , and . J. Low Power Electron., 8 (2): 248-258 (2012)A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (2): 287-291 (2019)