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Performance Evaluation of Reduced Bandwidth Multistage Interconnection Networks.

, and . ISCA, page 171-175. (1987)

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Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme., and . IEEE Trans. Computers, 36 (12): 1440-1449 (1987)A Parallel Algorithm for Cache Miss Ratio Evaluation., and . MASCOTS, page 79-82. The Society for Computer Simulation, (1993)Performance analysis of disk cache write policies., and . Microprocess. Microsystems, 19 (3): 121-130 (1995)An interleaved array-processing architecture., , and . AFIPS National Computer Conference, volume 53 of AFIPS Conference Proceedings, page 93-100. AFIPS Press, (1984)Analytical Estimation of Vector Access Performance in Parallel Memory Architectures., and . IEEE Trans. Computers, 42 (5): 616-624 (1993)A Multiaccess Frame Buffer Architecture.. IEEE Trans. Computers, 43 (5): 618-622 (1994)Increased Memory Performance During Vector Accesses Through the use of Linear Address Transformations.. IEEE Trans. Computers, 41 (2): 227-230 (1992)Address Transformations to Increase Memory Performance.. ICPP (1), page 237-241. Pennsylvania State University Press, (1989)An Efficient Memory System for the SIMD Construction of a Gaussian Pyramid., and . IEEE Trans. Parallel Distributed Syst., 7 (8): 855-860 (1996)Reducing Memory Contention in Shared Memory Multiprocessors.. ISCA, page 66-73. ACM, (1991)