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An interleaved array-processing architecture.

, , and . AFIPS National Computer Conference, volume 53 of AFIPS Conference Proceedings, page 93-100. AFIPS Press, (1984)

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Execution-Driven Simulation of Shared-Memory Multiprocessors., , , and . MASCOTS, page 83-86. The Society for Computer Simulation, (1993)Effective Pipelining of Digital Systems., and . IEEE Trans. Computers, 27 (9): 855-865 (1978)Augmented and pruned n log n multistaged networks: topology and performance., and . ICPP, page 10-12. IEEE Computer Society, (1982)A Note on the Iterative Decomposition of Finite Automata. Inf. Control., 15 (5): 424-435 (November 1969)Efficient simulation of cache memories., , and . WSC, page 1032-1041. ACM Press, (1989)Matrix Multiplication in an Interleaved Array Processing Architecture., and . ISCA, page 11-17. IEEE Computer Society, (1985)Asynchronous Control Arrays.. IEEE Trans. Computers, 23 (10): 1020-1029 (1974)Switching Strategies in Shuffle-Exchange Packet-Switched Networks., , and . IEEE Trans. Computers, 34 (2): 180-186 (1985)Performance Evaluation of Reduced Bandwidth Multistage Interconnection Networks., and . ISCA, page 171-175. (1987)A Modular Memory Scheme for Array Processing., and . ISCA, page 90-94. ACM, (1977)