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An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems., , and . ESTIMedia, page 21-26. IEEE Computer Society, (2006)High-level estimation methodology for designing the instruction cache memory of programmable embedded platforms., and . IET Comput. Digit. Tech., 3 (2): 205-221 (2009)A modified spiral search motion estimation algorithm and its embedded system implementation., , , , and . ISCAS (4), page 3347-3350. IEEE, (2005)Power, performance and area exploration of block matching algorithms mapped on programmable processors., , , , , , , and . ICIP (3), page 728-731. IEEE, (2001)Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors., , , , , , and . J. VLSI Signal Process., 44 (1-2): 153-171 (2006)A Modified Spiral Search Algorithm and its Embedded Hardware Implementation., , , and . IEC (Prague), page 375-378. Enformatika, Çanakkale, Turkey, (2005)Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems., and . VLSI-SoC (Selected Papers), volume 313 of IFIP Advances in Information and Communication Technology, page 251-270. Springer, (2008)FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer., and . Microprocess. Microsystems, 35 (3): 329-342 (2011)Data and instruction memory exploration of embedded systems for multimedia applications., , , , , and . ICASSP, page 1149-1152. IEEE, (2001)Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate., and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 505-515. Springer, (2007)