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Disambiguation of "Lonardo, Alessandro"

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Large Scale Low Power Computing System - Status of Network Design in ExaNeSt and EuroExa Projects.

, , , , , , , , , , , , and . CoRR, (2018)

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Alessandro Valeri

Fluorescence resonance energy transfer between multiple chromophores studied by single-molecule spectroscopy. Uni Düsseldorf, (2009)

Alessandro Zivelonghi

Alessandro Nova

Alessandro Topa

Alessandro Mirizzi

 

Other publications of authors with the same name

Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster., , , , , , , , , and . CoRR, (2013)ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces., , , , , , , , , and 2 other author(s). Future Gener. Comput. Syst., (2015)Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface., , , , , , , , , and . ReConFig, page 1-6. IEEE, (2013)Real-Time Cortical Simulations: Energy and Interconnect Scaling on Distributed Systems., , , , , , , , , and 4 other author(s). PDP, page 283-290. IEEE, (2019)Computing for LQCD: apeNEXT., , , , , , , , , and 9 other author(s). Comput. Sci. Eng., 8 (1): 18-29 (2006)Power, Energy and Speed of Embedded and Server Multi-Cores applied to Distributed Simulation of Spiking Neural Networks: ARM in NVIDIA Tegra vs Intel Xeon quad-cores., , , , , , , , , and . CoRR, (2015)APEnet+: high bandwidth 3D torus direct network for petaflops scale commodity clusters, , , , , , , , , and 2 other author(s). CoRR, (2011)A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report., , , , , , , , , and 2 other author(s). CoRR, (2013)'Mutual Watch-dog Networking': Distributed Awareness of Faults and Critical Events in Petascale/Exascale systems., , , , , , , , , and . CoRR, (2013)Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems., , , , , , , , , and . CoRR, (2013)