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Single cycle access cache for the misaligned data and instruction prefetch.

, , , , , , and . ASP-DAC, page 677-678. IEEE, (1997)

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SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture., , and . ICCD, page 419-425. IEEE Computer Society, (2003)Single cycle access cache for the misaligned data and instruction prefetch., , , , , , and . ASP-DAC, page 677-678. IEEE, (1997)Customization of a CISC Processor Core for Low-Power Applications., , , and . ICCD, page 152-. IEEE Computer Society, (1999)A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders., , and . ICCD, page 243-. IEEE Computer Society, (1999)Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies., , , and . ICCD, page 519-524. IEEE Computer Society, (2000)Issues on the Interface Synthesis between Intellectual Properties Operating at Different Clock Frequencies., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (8): 1937-1945 (2002)A New Single-Clock Flip-Clop for Half-Swing Clocking., , , and . ASP-DAC, page 117-120. IEEE Computer Society, (1999)Conforming inverted data store for low power memory., , and . ISLPED, page 91-93. ACM, (1999)SmartGlue: an interface controller with auto reconfiguration for field programmable computing machine., , , and . ASP-DAC, page 734-736. IEEE Computer Society, (2004)