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A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration.

, , , , , and . CICC, page 1-4. IEEE, (2015)

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A Scaling-Friendly Low-Power Small-Area ΔΣ ADC With VCO-Based Integrator and Intrinsic Mismatch Shaping Capability., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (4): 561-573 (2015)A purely-VCO-based single-loop high-order continuous-time ΣΔ ADC., , , and . ISCAS, page 926-929. IEEE, (2014)A 1.8mW 2MHz-BW 66.5dB-SNDR ΔΣ ADC using VCO-based integrators with intrinsic CLA., , and . CICC, page 1-4. IEEE, (2013)A 6-bit 0.81mW 700-MS/s SAR ADC with sparkle-code correction, resolution enhancement, and background window width calibration., and . CICC, page 1-4. IEEE, (2018)A pipelined SAR ADC reusing the comparator as residue amplifier., , , , , and . CICC, page 1-4. IEEE, (2017)Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs., , , , , , , and . IEICE Trans. Electron., 102-C (7): 509-519 (2019)A 10MHz-BW, 5.6mW, 70dB SNDR ΔΣ ADC using VCO-based integrators with intrinsic DEM., , and . ISCAS, page 2006-2009. IEEE, (2013)A 6-bit 0.81mW 700-MS/s SAR ADC with sparkle-code correction, resolution enhancement, and background window width calibration., and . CICC, page 1-4. IEEE, (2017)A 0.7-V 0.6-µW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction., , , , , and . IEEE J. Solid State Circuits, 52 (5): 1388-1398 (2017)A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction., , , , , and . CICC, page 1-4. IEEE, (2015)