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A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration.

Y. Yoon, K. Lee, S. Hong, X. Tang, L. Chen, and N. Sun. CICC, page 1-4. IEEE, (2015)

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Xiyuan Bai

Xiyuan Liu

Tang Tang

Xiyuan Zhou

Other publications of authors with the same name

A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM.J. Song, X. Tang, H. Luo, H. Zhang, X. Qiao, Z. Sun, X. Yang, Z. Wu, Y. Wang, R. Wang and 1 other author(s). IEEE J. Solid State Circuits, 59 (3): 842-854 (March 2024)A Two-Step ADC With a Continuous-Time SAR-Based First Stage.L. Shen, N. Sun, Y. Shen, Z. Li, W. Shi, X. Tang, S. Li, W. Zhao, M. Zhang, and Z. Zhu. IEEE J. Solid State Circuits, 54 (12): 3375-3385 (2019)A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC.J. Song, X. Tang, H. Luo, H. Zhang, X. Qiao, Z. Sun, X. Yang, Y. Wang, R. Wang, and R. Huang. CICC, page 1-2. IEEE, (2023)An NS-SAR ADC with Full-bit High-order Mismatch Shaped CDAC.X. Han, X. Tang, Z. Ma, X. Xu, Y. Suo, Q. Cai, and Y. Zhao. ISCAS, page 1-5. IEEE, (2023)A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp.M. Zhan, L. Jie, X. Tang, and N. Sun. ISSCC, page 164-166. IEEE, (2022)A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing.J. Song, Y. Wang, X. Tang, R. Wang, and R. Huang. A-SSCC, page 1-3. IEEE, (2021)A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation.X. Tang, Y. Shen, X. Xin, S. Liu, J. Cai, Z. Zhu, and N. Sun. VLSI Circuits, page 1-2. IEEE, (2020)16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation.J. Liu, X. Tang, W. Zhao, L. Shen, and N. Sun. ISSCC, page 258-260. IEEE, (2020)A pipelined SAR ADC reusing the comparator as residue amplifier.M. Gandara, W. Guo, X. Tang, L. Chen, Y. Yoon, and N. Sun. CICC, page 1-4. IEEE, (2017)S2-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits.M. Alawieh, X. Tang, and D. Pan. ASP-DAC, page 268-273. ACM, (2019)

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Disambiguation of "Tang, Xiyuan"

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A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration.

Please choose a person to relate this publication to

Xiyuan Bai

Xiyuan Liu

Xiyuan Liu

Tang Tang

Xiyuan Zhou

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tang, Xiyuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration.

Please choose a person to relate this publication to

Xiyuan Bai

Xiyuan Liu

Xiyuan Liu

Tang Tang

Xiyuan Zhou

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration.