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Noise tolerant ternary weight deep neural networks for analog in-memory inference., , , , , , , and . IJCNN, page 1-8. IEEE, (2021)Low Voltage Transient RESET Kinetic Modeling of OxRRAM for Neuromorphic Applications., , , , , , and . IRPS, page 1-6. IEEE, (2019)11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge., , , , , , , , , and 38 other author(s). ISSCC, page 212-214. IEEE, (2024)Analytic variability study of inference accuracy in RRAM arrays with a binary tree winner-take-all circuit for neuromorphic applications., , , , , , and . ESSDERC, page 62-65. IEEE, (2018)Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration., , , , , , , , , and 2 other author(s). ACM Trans. Design Autom. Electr. Syst., 27 (5): 46:1-46:21 (2022)A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration., , , , , , , and . CICC, page 1-2. IEEE, (2021)DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2022)