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Simultaneous Reduction of Dynamic and Static Power in Scan Structures, , , , и . CoRR, (2007)Sign bit reduction encoding for low power applications., , и . DAC, стр. 214-217. ACM, (2005)ByZFAD: a low switching activity architecture for shift-and-add multipliers., , и . SBCCI, стр. 179-183. ACM, (2006)Scan-Based Structure with Reduced Static and Dynamic Power Consumption., , , , и . J. Low Power Electron., 2 (3): 477-487 (2006)A Theoretical Framework for Quality Estimation and Optimization of DSP Applications Using Low-Power Approximate Adders., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (1): 327-340 (2019)OPLE: A Heuristic Custom Instruction Selection Algorithm Based on Partitioning and Local Exploration of Application Dataflow Graphs., , , и . ACM Trans. Embed. Comput. Syst., 14 (4): 72:1-72:23 (2015)Low Power Combinational Multipliers using Data-driven Signal Gating., и . APCCAS, стр. 1430-1433. IEEE, (2006)WL-VC SRAM: a low leakage memory circuit for deep sub-micron design., , и . ISCAS, IEEE, (2006)High performance circuit techniques for dynamic OR gates., , и . ISCAS, IEEE, (2006)Systematic test program generation for SoC testing using embedded processor., , , и . ISCAS (5), стр. 541-544. IEEE, (2003)