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BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (2): 302-306 (2009)A new merit function for custom instruction selection under an area budget constraint., , , , and . Des. Autom. Embed. Syst., 17 (1): 1-25 (2013)An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling., , , and . J. Zhejiang Univ. Sci. C, 13 (1): 58-70 (2012)Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (2): 125-134 (2007)An Efficient Clocking Scheme for On-Chip Communications., , , and . APCCAS, page 119-122. IEEE, (2006)Low Power Combinational Multipliers using Data-driven Signal Gating., and . APCCAS, page 1430-1433. IEEE, (2006)Simultaneous Reduction of Dynamic and Static Power in Scan Structures, , , , and . CoRR, (2007)Sign bit reduction encoding for low power applications., , and . DAC, page 214-217. ACM, (2005)ByZFAD: a low switching activity architecture for shift-and-add multipliers., , and . SBCCI, page 179-183. ACM, (2006)An efficent dynamic multicast routing protocol for distributing traffic in NOCs., , , , , , and . DATE, page 1064-1069. IEEE, (2009)