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Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process.

, , , , , , , , , , , , and . SP, page 1003-1020. IEEE, (2020)

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Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology., , , and . CICC, page 729-732. IEEE, (2007)Client-Cert HTTP Header Field., and . RFC, (July 2023)OAuth 2.0 Rich Authorization Requests., , and . RFC, (May 2023)OAuth 2.0 Mutual-TLS Client Authentication and Certificate-Bound Access Tokens., , , and . RFC, (February 2020)Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process., , , , , , , , , and 3 other author(s). SP, page 1003-1020. IEEE, (2020)A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems., , , , , , , , , and 18 other author(s). ISSCC, page 104-105. IEEE, (2007)ISA semantics for ARMv8-a, RISC-v, and CHERI-MIPS., , , , , , , , , and 4 other author(s). Proc. ACM Program. Lang., 3 (POPL): 71:1-71:31 (2019)OAuth 2.0 Step Up Authentication Challenge Protocol., and . RFC, (September 2023)OAuth 2.0 Demonstrating Proof of Possession (DPoP)., , , , , and . RFC, (September 2023)Verified Security for the Morello Capability-enhanced Prototype Arm Architecture., , , , , , , , and . ESOP, volume 13240 of Lecture Notes in Computer Science, page 174-203. Springer, (2022)