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Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process.

, , , , , , , , , , , , and . SP, page 1003-1020. IEEE, (2020)

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Rapid codesign of a soft vector processor and its compiler., and . FPL, page 1-4. IEEE, (2014)A spiking neural network on a portable FPGA tablet., , , and . FPL, page 1. IEEE, (2013)A Scoping Review Identifying the Need for Quality Research on the Use of Virtual Reality in Workplace Settings for Stress Management., , and . Cyberpsychology Behav. Soc. Netw., 23 (8): 506-518 (2020)Managing the FPGA memory wall: Custom computing or vector processing?, , , and . FPL, page 1-6. IEEE, (2013)Termination detection for fine-grained message-passing architectures., , , , , , , , and . ASAP, page 17-24. IEEE, (2020)A consistency checker for memory subsystem traces., , and . FMCAD, page 133-140. IEEE, (2016)A generic synthesisable test bench., and . MEMOCODE, page 128-137. IEEE, (2015)POETS: Distributed Event-Based Computing - Scaling Behaviour., , , , , , , and . PARCO, volume 36 of Advances in Parallel Computing, page 487-496. IOS Press, (2019)Pixel Behaviour Metrics for Dynamic Background Modelling with the Projected Difference Pattern Method., , , and . DICTA, page 25. IEEE Computer Society, (2005)Tinsel: A Manythread Overlay for FPGA Clusters., , and . FPL, page 375-383. IEEE, (2019)