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Disambiguation of "Soenen, Eric G."

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A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration.

, , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (9): 3373-3383 (2019)

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Johan Soenen

Freerk Erichsen

Ull Erich

Hauke Erichsen

Gerda Erich

 

Other publications of authors with the same name

A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (9): 3373-3383 (2019)A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs., , , , , , , and . IEEE J. Solid State Circuits, 53 (11): 3280-3292 (2018)A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS., , , , , and . ISSCC, page 198-199. IEEE, (2010)Practical Considerations for a Digital Inductive-Switching DC/DC Converter With Direct Battery Connect in Deep Sub-Micron CMOS., , , , and . IEEE J. Solid State Circuits, 47 (8): 1946-1959 (2012)A wide-range DC/DC converter with 2nd order digital compensation and direct battery connection in 40nm CMOS., , , , and . CICC, page 1-4. IEEE, (2011)A 1.8 V pseudo-differential switched-capacitor amplifier., , , and . CICC, page 373-376. IEEE, (1998)A digital low drop-out regulator with wide operating range in a 16nm FinFET CMOS process., , and . A-SSCC, page 1-4. IEEE, (2015)A 72.6 dB SNDR 14b 100 MSPS Ring Amplifier Based Pipelined SAR ADC with Dynamic Deadzone Control in 16 nm CMOS., and . CICC, page 1-4. IEEE, (2020)A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (9): 3352-3364 (2019)Integrated 105 dB SNR, 0.0031% THD+N Class-D Audio Amplifier With Global Feedback and Digital Control in 55 nm CMOS., , and . IEEE J. Solid State Circuits, 50 (8): 1764-1771 (2015)