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A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells.

, , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (12): 2226-2233 (2012)

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Hirokazu Kawaguchi

Hiroshi Murata

Hiroshi Kawabe

Hiroshi Kubota

Hiroshi Uchida

 

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