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Disambiguation of "Fujiwara, Hidehiro"

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A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.

, , , , , , , and . IEICE Trans. Electron., 91-C (4): 543-552 (2008)

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Esther Fujiwara

 

Other publications of authors with the same name

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications., , , , , , , , , and 6 other author(s). ISSCC, page 206-207. IEEE, (2017)A stable chip-ID generating physical uncloneable function using random address errors in SRAM., , , , , , and . SoCC, page 143-147. IEEE, (2012)A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry., , , , , , and . ISQED, page 438-441. IEEE, (2013)3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications., , , , , , , , and . VLSI Technology and Circuits, page 24-25. IEEE, (2022)34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell., , , , , , , , , and 13 other author(s). ISSCC, page 572-574. IEEE, (2024)A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing., , , , , , and . ISVLSI, page 107-112. IEEE Computer Society, (2007)A dynamic body-biased SRAM with asymmetric halo implant MOSFETs., , , , , , and . ISLPED, page 285-290. IEEE/ACM, (2011)Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application., , , , , and . ISQED, page 270-274. IEEE, (2012)A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs., , , , , , , and . ISSCC, page 236-238. IEEE, (2012)