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A circuit level implementation of an adaptive issue queue for power-aware microprocessors.

, , , , , and . ACM Great Lakes Symposium on VLSI, page 73-78. ACM, (2001)

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A circuit level implementation of an adaptive issue queue for power-aware microprocessors., , , , , and . ACM Great Lakes Symposium on VLSI, page 73-78. ACM, (2001)Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz., and . IEEE J. Solid State Circuits, 38 (4): 622-630 (2003)Constraint Solver for Generalized IC Layout.. IBM J. Res. Dev., 28 (5): 581-589 (1984)New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology., , , , and . ESSCIRC, page 309-312. IEEE, (2003)Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor., , , and . IEEE J. Solid State Circuits, 33 (4): 662-665 (1998)New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology., , , , and . ISLPED, page 168-171. ACM, (2003)An Adaptive Issue Queue for Reduced Power at High Performance., , , , , and . PACS, volume 2008 of Lecture Notes in Computer Science, page 25-39. Springer, (2000)Synchronous Interlocked Pipelines., , , , and . ASYNC, page 3-12. IEEE Computer Society, (2002)Tradeoffs in power-efficient issue queue design., , , , and . ISLPED, page 184-189. ACM, (2002)Early-Stage Definition of LPX: A Low Power Issue-Execute Processor., , , , , , , , , and 6 other author(s). PACS, volume 2325 of Lecture Notes in Computer Science, page 1-17. Springer, (2002)