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Disambiguation of "Gharehbaghi, Amir Masoud"

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System-Level Assertion-Based Performance Verification for Embedded Systems.

, , and . CSICC, volume 6 of Communications in Computer and Information Science, page 243-250. (2008)

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Amir Masoud Hossini

Amir Masoud Vahdat

Hassan Gharehbaghi

Masoud Ansari

Masoud Khiabanchian

 

Other publications of authors with the same name

Signal Selection Methods for Efficient Multi-Target Correction., , and . ISCAS, page 1-5. IEEE, (2019)Debugging from high level down to gate level., , and . DAC, page 627-630. ACM, (2009)Transaction-based debugging of system-on-chips with patterns., and . ICCD, page 186-192. IEEE Computer Society, (2009)A new approach for selecting inputs of logic functions during debug., and . ISQED, page 166-173. IEEE, (2017)Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults., , , and . ISCAS, page 1-4. IEEE, (2017)An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults., , and . VTS, page 1-6. IEEE, (2019)Global transaction ordering in Network-on-Chips for post-silicon validation., and . ISQED, page 284-289. IEEE, (2011)Specification and formal verification of power gating in processors., and . ISQED, page 604-610. IEEE, (2014)Formal verification guided automatic design error diagnosis and correction of complex processors., and . HLDVT, page 121-127. IEEE Computer Society, (2011)Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints., , , , and . ISCAS, page 1. IEEE, (2019)