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A Novel Division Algorithm and Architectures for Parallel and Sequential Processing.

, , , and . J. Circuits Syst. Comput., 14 (2): 281-296 (2005)

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A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC., , , , and . Int. J. Adapt. Resilient Auton. Syst., 4 (3): 1-24 (2013)Fuzzy classification of OpenCL programs targeting heterogeneous systems., , and . J. Intell. Fuzzy Syst., 39 (5): 7189-7202 (2020)A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications., , , , , , , , , and 1 other author(s). IEICE Trans. Inf. Syst., 88-D (7): 1369-1380 (2005)Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs., , , , and . Parallel Process. Lett., 18 (2): 291-306 (2008)A complete platform and toolset for system implementation on fine-grain reconfigurable hardware., , , , , , , , , and . Microprocess. Microsystems, 29 (6): 247-259 (2005)Data and instruction memory exploration of embedded systems for multimedia applications., , , , , and . ICASSP, page 1149-1152. IEEE, (2001)Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms., , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 1032-1035. Springer, (2003)Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications., , , and . IPDPS, IEEE, (2006)Power, performance and area exploration of block matching algorithms mapped on programmable processors., , , , , , , and . ICIP (3), page 728-731. IEEE, (2001)Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors., , , , , , and . J. VLSI Signal Process., 44 (1-2): 153-171 (2006)