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A Testable/Fault Tolerant FFT Processor Design.

, , and . Asian Test Symposium, page 429-. IEEE Computer Society, (2000)

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Fault-Aware Dependability Enhancement Techniques for Flash Memories., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (3): 634-645 (2020)Efficient test and repair architectures for 3D TSV-based random access memories., , , and . VLSI-DAT, page 1-4. IEEE, (2013)Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs., , , and . VLSI-DAT, page 1-4. IEEE, (2015)Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators., , , , , and . ATS, page 49-53. IEEE, (2022)A built-in supply current test circuit for electrical interconnect tests of 3D ICs., , , and . 3DIC, page 1-6. IEEE, (2014)Integrated Progressive Built-In Self-Repair (IPBISR) Techniques for NAND Flash Memory., and . ITC-Asia, page 1-6. IEEE, (2023)A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume., , , , and . ISCIT, page 1-5. IEEE, (2017)Combinational circuit fault diagnosis using logic emulation., , , , and . ISCAS (5), page 549-552. IEEE, (2003)Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs., , and . Asian Test Symposium, page 308-313. IEEE Computer Society, (2012)A Multi-Faceted Approach towards Spam-Resistible Mail., , , , and . PRDC, page 208-218. IEEE Computer Society, (2005)