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Disambiguation of "Karfa, Chandan"

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Translation Validation of Loop Invariant Code Optimizations Involving False Computations.

, , and . VDAT, volume 711 of Communications in Computer and Information Science, page 767-778. Springer, (2017)

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Chandan Maity

Chandan Mukherjee

Chandan Roy

Chandan Das

Chandan Goswami

 

Other publications of authors with the same name

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking., , , , , , , , , and 25 other author(s). CoRR, (2020)Verification of Scheduling of Conditional Behaviors in High-Level Synthesis., and . IEEE Trans. Very Large Scale Integr. Syst., 28 (7): 1638-1651 (2020)Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples., , and . VLSID, page 377-382. IEEE, (2019)Verification of Scheduling in High-level Synthesis., , , , and . ISVLSI, page 141-146. IEEE Computer Society, (2006)A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques., , , and . ISED, page 67-71. IEEE, (2012)Register Sharing Verification During Data-Path Synthesis., , , and . ICCTA, page 135-140. IEEE Computer Society, (2007)Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC., and . IEEE Embed. Syst. Lett., 14 (2): 67-70 (2022)TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems., , , and . ACM Trans. Design Autom. Electr. Syst., 28 (6): 99:1-99:22 (November 2023)BLAST: Belling the Black-Hat High-Level Synthesis Tool., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 3661-3672 (2022)Quantifying Information Leakage for Security Verification of Compiler Optimizations., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 4385-4396 (2022)