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A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip.

, , , , , , and . IEEE J. Solid State Circuits, 59 (2): 616-625 (February 2024)

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MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip., , , , , , and . IEEE J. Solid State Circuits, 56 (7): 2270-2280 (2021)A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip., , , , , , and . IEEE J. Solid State Circuits, 59 (2): 616-625 (February 2024)CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (9): 3078-3091 (September 2023)CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement., , , , and . DAC, page 1093-1098. IEEE, (2021)MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation., , , , , , and . CICC, page 1-2. IEEE, (2022)A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip., , , , and . ISCAS, page 1-5. IEEE, (2023)25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip., , , , , and . ISSCC, page 394-396. IEEE, (2020)